Look-up table based FPGAs have migrated from a niche technology for design prototyping to a valuable end-product component and, in some cases, a replacement for general purpose processors and ASICs alike. One way architects have bridged the performance gap between FPGAs and ASICs is through the inclusion of specialized components such as multipliers, RAM modules, and microcontrollers. Another dedicated structure that has become standard in reconfigurable fabrics is the arithmetic carry chain. Currently, it is only used to map arithmetic operations as identified by HDL macros. For non-arithmetic operations, it is an idle but potentially powerful resource.
What is needed is a method of creating logic chains using the arithmetic carry chain in reconfigurable fabrics such as FPGAs and a method to provide for depth-optimal mapping of the logic chains.
Therefore, it is a primary object, feature, or advantage of the present invention to improve over the state of the art.
It is a further object, feature, or advantage of the present invention to provide a formal logic chain definition that encompasses both arithmetic and non-arithmetic operations.
It is a still further object, feature, or advantage of the present invention to create generic logic chains in polynomial time without HDL arithmetic chain macros.
Yet another object, feature, or advantage of the present invention is eliminate or reduce an area trade-off associated with the exclusivity constraint of current FPGA carry chain architectures.
A still further object, feature, or advantage of the present invention is to provide for creating logic chains without HDL.
One or more of these and/or other objects, features, or advantages of the present invention will become apparent from the specification and claims that follow.